а пардон, на другом форуме было: LOCK HALT FLAG
Bit 7 of the seconds register is defined as the clock halt (CH) flag. When this bit is set to logic 1, the clock oscillator
is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less than 100nA. When
this bit is written to logic 0, the clock will start. The initial power-on state is not defined
короче, при первом включении часов этот LOCK HALT FLAG не установлен и его нужно установить в 0 - но хз как.